脉冲边沿的特性：两侧电平发生了变化
思路：设计两个或多个一位的寄存器，用来接收被检测的信号，系统时钟来一次记一次输入信号，如果用了两个寄存器直接异或就可以了。
module edge_detect(input clk,input rst_n, input data_in, output raising_edge_detect, output falling_edge_detect, output double_edge_detect);reg data_in_d1;reg data_in_d2;always @ (posedge clk,negedge rst_n)beginif(!rst_n)begin data_in_d1 <= 1'b0; data_in_d2 <= 1'b0; end elsebegin data_in_d1 <= data_in; data_in_d2 <= data_in_d1;end end assign raising_edge_detect = data_in_d1 & (~data_in_d2);//上升沿assign falling_edge_detect = ~data_in_d1 & data_in_d2;//下降沿assign double_edge_detect = data_in_d1 ^ data_in_d2;//双边沿endmodule
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